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Sub-micron Cell Design and Process Fault Tolerance of Source Buried Trench Silicon Carbide VDMOSFET
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Abstract
This paper presents a novel silicon carbide vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET) based on a buried trench U-shaft structure, aiming to address the dual technical challenges of the size limit of traditional VDMOSFET cells and high defect rates in UMOSFET processes. By burying the U-shaft beneath the isolation oxide layer and using Ti/Al/W ohmic contact alloying technology, the width of the double-channel cell has been reduced from 6 μm in conventional structures to 4.5 μm (single channel 2.25 μm). The structure significantly enhances the tolerance to U-shaft etching morphology: the allowable range of sidewall inclination extends from 85°-95° in traditional UMOSFET to 75°-105°, and the sub-trench defect tolerance depth increases from <0.1 μm to 0.3 μm. This study demonstrates that the buried trench U-shaft design provides a technical path for high-power-density silicon carbide devices that balances performance and process feasibility.
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How to cite this paper
Sub-micron Cell Design and Process Fault Tolerance of Source Buried Trench Silicon Carbide VDMOSFET
How to cite this paper: Yili Xu, Xin Li, Xiaodong Yin, Guowei Zhang, Jingyi Li, Qianqian Liu. (2025). Sub-micron Cell Design and Process Fault Tolerance of Source Buried Trench Silicon Carbide VDMOSFET. Engineering Advances, 5(2), 76-81.
DOI: http://dx.doi.org/10.26855/ea.2025.04.006
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